本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益

---

题目链接：Tb/clock - HDLBits

`timescale 1ps/1ps
module top_module ( );
    parameter time_period = 10 ; 
    reg clk ; 
    initial clk = 0 ; 
    always  begin
        # (time_period / 2) clk = ~clk ; 
    end

    dut u1(
        .clk(clk)
    );
endmodule

---

题目链接：Tb/tb1 - HDLBits

module top_module ( output reg A, output reg B );//

    // generate input patterns here
    initial begin
        A = 0 ; 
        B = 0 ; 
        # 10 ; 
        A = 1 ; 
        B = 0 ; 
        # 5 ; 
        A = 1 ; 
        B = 1 ;    
        # 5 ; 
        A = 0 ; 
        B = 1 ; 
        # 20 ; 
        A = 0 ; 
        B = 0 ; 
    end

endmodule

---

题目链接：Tb/and - HDLBits

`timescale 1ps/1ps

module top_module();
    reg [1:0] in ; 
    wire out ; 

    initial begin 
        in = 2'b00 ; 
        # 10 ; 
        in = 2'b01 ; 
        # 10 ; 
        in = 2'b10 ; 
        # 10 ; 
        in = 2'b11 ; 
    end

    andgate u1(
        .in(in),
        .out(out) 
    );

endmodule

---

题目链接：Tb/tb2 - HDLBits

`timescale 1ps/1ps
module top_module();
    reg clk, in ; 
    reg [2:0] s ; 
    wire out ; 
    initial begin
        clk = 0 ; 
        in = 0 ; 
        s = 2 ; 
        # 10 
        s = 6 ; 
        # 10 
        in = 1 ; 
        s = 2 ; 
        # 10 
        in = 0 ; 
        s = 7 ; 
        # 10 ; 
        in = 1 ; 
        s = 0 ; 
        # 30 ; 
        in = 0 ; 
    end

    always  begin
        # 5 ; 
        clk = ~clk ;
    end

    q7 u1(
        .clk(clk), 
        .s(s),
        .in(in), 
        .out(out) 
    );

endmodule

---

题目链接：Tb/tff - HDLBits

module top_module ();
    reg clk ;
    reg reset ; 
    reg t ;
    wire q ;

    tff u1(
        .clk(clk),
        .reset(reset),
        .t(t),
        .q(q)
    );

    initial begin
        clk = 1'b0 ; 
        forever begin
            # 5 ;
            clk = ~clk ;
        end
    end

    initial begin
        reset = 1'b0 ; 
        # 3 ; 
        reset = 1'b1 ; 
        # 10 ; 
        reset = 1'b0 ;  
    end

    always @(posedge clk) begin
        if (reset) t <= 1'b0 ;
        else t <= 1'b1 ; 
    end


endmodule